Some details of future AMD "Carrizo" processors

I'm glad to see AMD is still aggressively chasing Intel.

AMD in January announced their latest family of desktop processors, based on "Kaveri" core, and the company is hard at work on the next generation of APUs, due in 2015.

The future Accelerated Processing Units for desktop and mobile computers will be codenamed "Carrizo", and they will be built on "Excavator" microarchitecture. Some details of these products were revealed this week by "Bright Side of News" hardware news site. They got hands on a document, titled "Preliminary BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h Models 60h-6Fh Processors", that described internal architecture of Carrizo APUs.

Current "Steamroller" microarchitecture uses various optimizations to improve processor IPC, and "Excavator" is expected to improve it even further. The guide does not go into details of these optimizations, but mentions a few new features, that should enhance general performance and power consumption of Carrizo processors. That includes support for new instructions and DDR4 memory, integration of the Fusion Controller Hub (FCH), and upgrade of general purpose PCI-Express interface to version 3.0.

It was already reported that Carrizo APUs will add AVX2, BMI2, MOVBE and RDRAND instructions, as well as TSX on some SKUs. The processors will come with a memory controller, that will work with DDR3 and DDR4 memory. The controller is going to support registered DIMMs and ECC, although these features might be enabled only on server and embedded products. The document does not state the maximum data rates for DDR4 memory, and the DDR3 rate depends on the socket. While the maximum rate is still 2400 MHz, socket SP2 APUs will be limited to 2133 MHz, and socket FP4 APUs will support up to 1866 MHz. Carrizo server parts will add support for "data poisoning" RAS feature, that will allow them to continue processing even when they encounter certain uncorrectable data errors.

The processors for socket FP4 will be produced in a BGA-type package. A new feature of these products will be an integrated Fusion Controller Hub (FCH) with 2 SATA 6GB/s ports and 12 USB ports, including 4 ports with USB 3.0 support. The FCH will also have an SD card interface, 2 UART interfaces and legacy I/O. The FP4 chips will be used in mobile computers and other low power devices.

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